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rev. 1.2 5/10 copyright ? 2010 by silicon laboratories si570/si571 si570/si571 10 mh z to 1.4 gh z i 2 c p rogrammable xo/vcxo features applications description the si570 xo/si571 vcxo utilizes silicon laboratories? advanced dspll ? circuitry to provide a low-jitter clock at any frequency. the si570/si571 are user-programmable to any output frequency from 10 to 945 mhz and select frequencies to 1400 mhz with <1 ppb resolution. the device is programmed via an i 2 c serial interface. unlike traditional xo/vcxos where a different crystal is required for each output frequency, the si57x uses one fixed- frequency crystal and a dspll clock synthesis ic to provide any-frequency operation. this ic-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. in addition, dspll clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. functional block diagram ? any programmable output frequencies from 10 to 945 mhz and select frequencies to 1.4 ghz ? i 2 c serial interface ? 3rd generation dspll ? with superior jitter performance ? 3x better frequency stability than saw-based oscillators ? internal fixed crystal frequency ensures high reliability and low aging ? available lvpecl, cmos, lvds, and cml outputs ? industry-standard 5x7 mm package ? pb-free/rohs-compliant ? 1.8, 2.5, or 3.3 v supply ? sonet/sdh ? xdsl ? 10 gbe lan/wan ? low-jitter clock generation ? optical modules ? clock and data recovery fixed frequency xo 10-1400 mhz dspll ? clock synthesis clk- clk+ scl gnd oe v dd sda v c adc si571 only ordering information: see page 24. pin assignments: see page 23. (top view) si5602 si570 si571 1 2 3 6 5 4 nc gnd oe v dd clk+ clk? sda scl 8 7 1 2 3 6 5 4 v c gnd oe v dd clk+ clk? sda scl 8 7
si570/si571 2 rev. 1.2
si570/si571 rev. 1.2 3 t able of c ontents section pag e 1. detailed block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1. programming a new output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2. i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4. serial port regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. si570 (xo) pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6. si571 (vcxo) pin d escriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 8. si57x mark speci fication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. outline diagram and suggest ed pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. 8-pin pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
si570/si571 4 rev. 1.2 1. detailed block diagrams figure 1. si570 detailed block diagram figure 2. si571 detailed block diagram frequency control control interface nvm hs_div n1 + dco rfreq clkout+ clkout? v dd gnd f xtal f osc m sda oe scl ram frequency control control interface nvm hs_div n1 + dco adc rfreq vcadc v c clkout+ clkout? v dd gnd f xtal f osc m sda oe scl ram
si570/si571 rev. 1.2 5 2. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max units supply voltage 1 v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 1.8 v option 1.71 1.8 1.89 supply current i dd output enabled lvpecl cml lvds cmos ? ? ? ? 120 108 99 90 130 117 108 98 ma tristate mode ? 60 75 output enable (oe) 2 , serial data (sda), serial clock (scl) v ih 0.75 x v dd ?? v v il ??0.5 operating temperature range t a ?40 ? 85 oc notes: 1. selectable parameter specified by part number. see section "7. ordering information" on page 24 for further details. 2. oe pin includes a 17 k ? pullup resistor to v dd . see ?7.ordering information?. table 2. v c control voltage input parameter symbol test condition min typ max units control voltage tuning slope 1,2,3 k v v c 10 to 90% of v dd ? 33 45 90 135 180 356 ? ppm/v control voltage linearity 4 l vc bsl ?5 1 +5 % incremental ?10 5 +10 modulation bandwidth bw 9.3 10.0 10.7 khz v c input impedance z vc 500 ? ? k ? nominal control voltage v cnom @ f o ?v dd /2 ? v control voltage tuning range v c 0v dd v notes: 1. positive slope; selectable option by part number. see "7. ordering information" on page 24. 2. for best jitter and phase noise performance, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. k v variation is 10% of typical values. 4. bsl determined from deviation from best straight line fit with v c ranging from 10 to 90% of v dd . incremental slope is determined with v c ranging from 10 to 90% of v dd .
si570/si571 6 rev. 1.2 table 3. clk output frequency characteristics parameter symbol test condition min typ max units programmable frequency range 1,2,3 f o lvpecl/lvds/cml 10 ? 1417.5 mhz cmos 10 ? 160 temperature stability 1,4 t a = ?40 to +85 oc ?20 ?50 ?100 ? ? ? +20 +50 +100 ppm initial accuracy ?1.5? ppm aging f a frequency drift over first year ? ? 3 ppm frequency drift over 15 year life ? ? 10 ppm total stability temp stability = 20 ppm ? ? 31.5 ppm temp stability = 50 ppm ? ? 61.5 ppm absolute pull range 1,4 apr 25 ? 375 ppm power up time 5 t osc ??10ms notes: 1. see section "7. ordering information" on page 24 for further details. 2. specified at time of order by part number. three speed grades available: grade a covers 10 to 945 mhz, 970 to 1134 mhz, and 1213 to 1417.5 mhz. grade b covers 10 to 810 mhz. grade c covers 10 to 280 mhz. 3. nominal output frequency set by v cnom =1/2xv dd . 4. selectable parameter specified by part number. 5. time from power up or tristate mode to f o .
si570/si571 rev. 1.2 7 table 4. clk output levels and symmetry parameter symbol test condition min typ max units lvpecl output option 1 v o mid-level v dd ? 1.42 ? v dd ? 1.25 v v od swing (diff) 1.1 ? 1.9 v pp v se swing (single-ended) 0.55 ? 0.95 v pp lvds output option 2 v o mid-level 1.125 1.20 1.275 v v od swing (diff) 0.5 0.7 0.9 v pp cml output option 2 v o 2.5/3.3 v option mid-level ? v dd ? 1.30 ? v 1.8 v option mid-level ? v dd ? 0.36 ? v pp v od 2.5/3.3 v option swing (diff) 1.10 1.50 1.90 v 1.8 v option swing (diff) 0.35 0.425 0.50 v pp cmos output option 3 v oh i oh =32ma 0.8 x v dd ? v dd v v ol i ol =32ma ? ? 0.4 rise/fall time (20/80%) t r, t f lvpecl/lvds/cml ? ? 350 ps cmos with c l =15pf ? 1 ? ns symmetry (duty cycle) sym lvpecl: v dd ? 1.3 v (diff) lvds: 1.25 v (diff) cmos: v dd /2 45 ? 55 % notes: 1. 50 ? to v dd ? 2.0 v. 2. r term =100 ? (differential). 3. c l =15pf table 5. clk output phase jitter (si570) parameter symbol test condition min typ max units phase jitter (rms)* for f out > 500 mhz ? j 12 khz to 20 mhz (oc-48) ? 0.25 0.40 ps 50 khz to 80 mhz (oc-192) ? 0.26 0.37 phase jitter (rms)* for f out of 125 to 500 mhz ? j 12 khz to 20 mhz (oc-48) ? 0.36 0.50 ps 50 khz to 20 mhz (oc-192) ? 0.34 0.42 phase jitter (rms) for f out of 10 to 160 mhz cmos output only ? j 12 khz to 20 mhz (oc-48) ? 0.62 ? ps 50 khz to 80 mhz (oc-192) ? 0.61 ? *note: refer to an256 for further information.
si570/si571 8 rev. 1.2 table 6. clk output phase jitter (si571) parameter symbol test condition min typ max units phase jitter (rms) 1,2,3 for f out > 500 mhz ? j kv = 33 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.26 0.26 ? ? ps kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.27 0.26 ? ? kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.32 0.26 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.40 0.27 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.49 0.28 ? ? kv = 356 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.87 0.33 ? ? notes: 1. differential modes: lvpecl/lvds/cml. refer to an255, an256, and an266 for further information. 2. for best jitter and phase noise performance, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. see ?an255: replacing 622 mhz vcso devices with the si550 vcxo? for comparison highlighting power supply rejection (psr) advantage of si55x versus saw-based solutions. 4. single ended mode: cmos. refer to the following application notes for further information: ?an255: replacing 622 mhz vcso device with the si55x vcxo? ?an256: integrated phase noise? ?an266: vcxo tuning slope (kv), stability, and absolute pull range (apr)?
si570/si571 rev. 1.2 9 phase jitter (rms) 2,4 for f out 10 to 160 mhz cmos output only ? j kv = 33 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.63 0.62 ? ? ps kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.63 0.62 ? ? kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.67 0.66 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.74 0.72 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.83 0.8 ? ? kv = 356 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 1.26 1.2 ? ? table 6. clk output phase jitter (si571) (continued) parameter symbol test condition min typ max units notes: 1. differential modes: lvpecl/lvds/cml. refer to an255, an256, and an266 for further information. 2. for best jitter and phase noise performance, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. see ?an255: replacing 622 mhz vcso devices with the si550 vcxo? for comparison highlighting power supply rejection (psr) advantage of si55x versus saw-based solutions. 4. single ended mode: cmos. refer to the following application notes for further information: ?an255: replacing 622 mhz vcso device with the si55x vcxo? ?an256: integrated phase noise? ?an266: vcxo tuning slope (kv), stability, and absolute pull range (apr)?
si570/si571 10 rev. 1.2 phase jitter (rms) 1,2,3 for f out of 125 to 500 mhz ? j kv = 33 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.37 0.33 ? ? ps kv = 45 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.37 0.33 ? ? kv = 90 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.43 0.34 ? ? kv = 135 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.50 0.34 ? ? kv = 180 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.59 0.35 ? ? kv = 356 ppm/v 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 1.00 0.39 ? ? table 7. clk output period jitter parameter symbol test condition min typ max units period jitter* j per rms ? 2 ? ps peak-to-peak ? 14 ? *note: any output mode, including cmos, lvpecl, lvds, cml. n = 1000 cycles. refer to ?an279: estimating period jitter from phase noise? fo r further information. table 6. clk output phase jitter (si571) (continued) parameter symbol test condition min typ max units notes: 1. differential modes: lvpecl/lvds/cml. refer to an255, an256, and an266 for further information. 2. for best jitter and phase noise performance, always choose the smallest k v that meets the application?s minimum apr requirements. see ?an266: vcxo tuning slope (k v ), stability, and absolute pull r ange (apr)? for mo re information. 3. see ?an255: replacing 622 mhz vcso devices with the si550 vcxo? for comparison highlighting power supply rejection (psr) advantage of si55x versus saw-based solutions. 4. single ended mode: cmos. refer to the following application notes for further information: ?an255: replacing 622 mhz vcso device with the si55x vcxo? ?an256: integrated phase noise? ?an266: vcxo tuning slope (kv), stability, and absolute pull range (apr)?
si570/si571 rev. 1.2 11 table 8. typical clk output phase noise (si570) offset frequency (f) 120.00 mhz lvds 156.25 mhz lvpecl 622.08 mhz lvpecl units 100 hz 1khz 10 khz 100 khz 1mhz 10 mhz 100 mhz ?112 ?122 ?132 ?137 ?144 ?150 n/a ?105 ?122 ?128 ?135 ?144 ?147 n/a ?97 ?107 ?116 ?121 ?134 ?146 ?148 dbc/hz table 9. typical clk output phase noise (si571) offset frequency (f) 74.25 mhz 90 ppm/v lvpecl 491.52 mhz 45 ppm/v lvpecl 622.08 mhz 135 ppm/v lvpecl units 100 hz 1khz 10 khz 100 khz 1mhz 10 mhz 100 mhz ?87 ?114 ?132 ?142 ?148 ?150 n/a ?75 ?100 ?116 ?124 ?135 ?146 ?147 ?65 ?90 ?109 ?121 ?134 ?146 ?147 dbc/hz table 10. absolute maximum ratings parameter symbol rating units supply voltage, 1.8 v option v dd ?0.5 to +1.9 v supply voltage, 2.5/3.3 v option v dd ?0.5 to +3.8 v input voltage v i ?0.5 to v dd + 0.3 v storage temperature t s ?55 to +125 oc esd sensitivity (hbm, per jesd22-a114) esd >2500 v soldering temperature (lead-free profile) t peak 260 oc soldering temperature time @ t peak (lead-free profile) t p 20?40 seconds notes: 1. stresses beyond the absolute maximum ratings may cause pe rmanent damage to the device. functional operation or specification compliance is not implied at these conditions. 2. the device is compliant with jedec j-std-020c. refer to si5xx packaging faq available for download at www.silabs.com/vcxo for further information, including soldering profiles.
si570/si571 12 rev. 1.2 table 11. environmental compliance the si570/571 meets the following qualification test requirements. parameter conditions/test method mechanical shock mil-std-883, method 2002 mechanical vibration mil-std-883, method 2007 solderability mil-std -883, method 2003 gross & fine leak mil-std-883, method 1014 resistance to solder heat mil-std-883, method 2036 table 12. programming constraints and timing (v dd = 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test co ndition min typ max unit output frequency range cko f hs_div x n1 > = 6 10 ? 945 mhz hs_div x n1 = 5 n1 = 1 970 ? 1134 mhz hs_div = 4 n1 = 1 1.2125 ? 1.4175 ghz frequency reprogramming resolution m res 114.285 mhz ? 0.09 ? ppb internal oscilla tor frequency f osc 4850 ? 5670 mhz internal crystal frequency accuracy f xtal maximum variation is 2000 ppm ? 114.285 ? mhz delta frequency for continu- ous output from center frequency ?3500 ? +3500 ppm unfreeze to newfreq timeout 10 ms settling time for small frequency change <3500 ppm from center frequency ??100s settling time for large frequency change >3500 ppm from center frequency after setting newfreq bit ??10 ms
si570/si571 rev. 1.2 13 3. functional description the si570 xo and the si571 vcxo are low-jitter oscillators ideally suited for applicatio ns requiring programmable frequencies. the si57x can be programmed to generate virtually any output clock in the range of 10 mhz to 1.4 ghz. output jitter performance exceeds the strict requirements of high- speed communication systems including oc-192/stm- 64 and 10 gigabit ethernet (10 gbe). the si57x consists of a digitally-controlled oscillator (dco) based on silicon labo ratories' third-generation dspll technology, which is driven by an internal fixed- frequency crystal reference. the device's default output frequency is set at the factory and can be reprogrammed through the two-wire i 2 c serial port. once the device is powered down, it will return to its factory-set default output frequency. while the si570 outputs a fixed frequency, the si571 has a pullable output frequency using the voltage control input pin. this makes the si571 an ideal choice for high-performance, low-jitter, phase-locked loops. 3.1. programming a new output frequency the output frequency (f out ) is determined by programming the dco frequency (f dco ) and the device's output dividers (hs_div, n1). the output frequency is calculated using the following equation: the dco frequency is adjustable in the range of 4.85 to 5.67 ghz by setting the high-resolution 38-bit fractional multiplier (rfreq). the dco frequency is the product of the internal fixed-frequency crystal (f xtal ) and rfreq. the 38-bit resolution of rfreq allows the dco frequency to have a programmable frequency resolution of 0.09 ppb. as shown in figure 3, the device allows reprogramming of the dco frequency up to 3500 ppm from the center frequency configuration without interruption to the output clock. changes greater than the 3500 ppm window will cause t he device to recalibrate its internal tuning circuitry, forcing the output clock to momentarily stop and start at any arbitrary point during a clock cycle. this re-calibration process establishes a new center frequency and can take up to 10 ms. circuitry receiving a clock from the si57x device that is sensitive to glitches or runt pulses may have to be reset once the recalibration proc ess is complete. 3.1.1. reconfiguring the output clock for a small change in frequency for output changes less than 3500 ppm from the center frequency configuration, the dco frequency is the only value that needs reprogramming. since f dco =f xtal x rfreq, and that f xtal is fixed, changing the dco frequency is as simple as reconfiguring the rfreq value as outlined below: 1. using the serial port, read the current rfreq value (registers 0x08?0x12). 2. calculate the new value of rfreq given the change in frequency. 3. using the serial port, write the new rfreq value (registers 0x08?0x12). example: an si570 generating a 148.35 mhz clock must be reconfigured "on-the-fly" to generate a 148.5 mhz clock. this represents a change of +1011.122 ppm, which is well within the 3500 ppm window. figure 3. dco frequency range f out f dco output dividers ---------------------------------------- - f xtal rfreq ? hsdiv n1 ? ------------------------------------------ - == rfreq new rfreq current f out_new f out_current ------------------------- ? = 4.85 ghz 5.67 ghz center frequency configuration -3500 ppm +3500 ppm small frequency changes can be made ?on-the-fly? without interruption to the output clock
si570/si571 14 rev. 1.2 a typical frequency configuration for this example: rfreq current = 0x2ebb04ce0 f out_current =148.35mhz f out_new =148.50mhz calculate rfreq new to change the output frequency from 148.35 mhz to 148.5 mhz: note that performing calculations with rfreq requires a minimum of 38-bit arithmetic precision. even relatively small changes in output frequency may require writing more than 1 rfreq register. such multi- register rfreq writes can impact the output clock frequency on a register-by-register basis during updating. interim changes to the ou tput clock during rfreq writes can be prevented by using the following procedure: 1. freeze the ?m? value (set register 135 bit 5 = 1). 2. write the new frequency configuration (rfreq). 3. unfreeze the ?m? value (set register 135 bit 5 = 0) 3.1.2. reconfiguring the output clock for large changes in output frequency for output frequency changes outside of 3500 ppm from the center frequency, it is likely that both the dco frequency and the output dividers need to be reprogrammed. note that changing the dco frequency outside of the 3500 ppm window will cause the output to momentarily stop and restart at any arbitrary point in a clock cycle. devices sensitive to glitches or runt pulses may have to be reset once reconfiguration is complete. the process for reconfiguring the output frequency outside of a 3500 ppm window is shown below: 1. using the serial port, read the current values for rfreq, hsdiv, and n1. 2. calculate f xtal for the device. note that because of slight variations of the internal crystal frequency from one device to another, each device may have a different rfreq value or possibly even different hsdiv or n1 values to maintain the same output frequency. it is necessary to calculate f xtal for each device. once f xtal has been determined, new values for rfreq, hsdiv, and n1 are calculated to generate a new output frequency (f out_new ). new values can be calculated manually or with the si57x-evb software, which provides a user-friendly application to help find the optimum values. the first step in manually calculating the frequency configuration is to determine new frequency divider values (hsdiv, n1). given the desired output frequency (fout_new), find the frequenc y divider values that will keep the dco oscillation freq uency in the range of 4.85 to 5.67 ghz. valid values of hsdiv are 4, 5, 6, 7, 9 or 11. n1 can be selected as 1 or any even number up to 128 (i.e. 1, 2, 4, 6, 8, 10 ? 128). to help minimize the device's power consumption, the divider values should be selected to keep the dco's oscillati on frequency as low as possible. the lowest value of n1 with the highest value of hs_div also results in the best power savings. once hs_div and n1 have been determined, the next step is to calculate the re ference frequency multiplier (rfreq). rfreq is programmable as a 38-bit binary fractional frequency multiplier with the fi rst 10 most significant bits (msbs) representing the integer portion of the multiplier, and the 28 least significant bits (lsbs) representing the fractional portion. before entering a fractio nal number into the rfreq register, it must be converted to a 38-bit integer using a bitwise left shift operation by 28 bits, which effectively multiplies rfreq by 2 28 . example: rfreq = 46.043042064d multiply rfreq by 2 28 = 12359584992.1 discard the fractional portion = 12359584992 convert to hexadecimal = 02e0b04ce0h in the example above, t he multiplication operation requires 38-bit precision. if 38-bit arithmet ic precision is not available, then the fractional portion can be separated from the integer and shifted to the left by 28- bits. the result is concatenated with the integer portion to form a full 38-bit word. an example of this operation is shown in figure 4. rfreq new 0x2ebb04ce0 148.50 mhz 148.35 mhz ------------------------------- - ? 0x2ec71d666 = = f xtal f out hsdiv ? n1 ? rfreq --------------------------------------------------- = f dco_new f out_new hsdiv new ? n1 new ? = rfreq new f dco_new f xtal ---------------------- -=
si570/si571 rev. 1.2 15 figure 4. example of rfreq decimal to hexadecimal conversion once the new values for rfreq, hsdiv, and n1 are determined, they can be written directly into the device from the serial port using the following procedure: 1. freeze the dco (bit 4 of register 137) 2. write the new frequency configuration (rfreq, hs_div, n1) 3. unfreeze the dco and assert the newfreq bit (bit 6 of register 135) within the maximum unfreeze to newfreq timeout specified in table 12, ?programming constraints and timing,? on page 12. the process of freezing and unfreezing the dco will cause the output clock to momentarily stop and start at any arbitrary point during a clock cycle. this process can take up to 10 ms. circuitry that is sensitive to glitches or runt pulses may have to be reset after the new frequency configuration is written. example: an si570 generating 156.25 mhz must be re-configured to generate a 161.1328125 mhz clock (156.25 mhz x 66/64). this frequency change is greater than 3500 ppm. f out =156.25mhz read the current values for rfreq, hs_div, n1: rfreq current = 0x2bc011eb8h = 11744124600d, 11744124600d x 2 28 = 43.7502734363d hs_div = 4 n1 = 8 calculate f xtal , f dco_current given f out_new = 161.1328125 mhz, choose output dividers that will keep f dco within the range of 4.85 to 5.67 ghz. in this case, keeping the same output dividers will still keep f dco within its range limits: calculate the new value of rfreq given the new dco frequency: 46.043042064 convert integer portion to a 10-bit binary number 46 = 00 0010 1110b concatenate the two results 00 0010 1110 0000 1011 0000 0100 1100 1110 0000b convert to hex 02e0b04ce0h multiply the fractional portion by 2 28 .043042064 x 2 28 = 11554016.077 truncate the remaining fractional portion = 11554016 convert to a 28-bit binary number (pad 0s on the left) 0000 1011 0000 0100 1100 1110 0000 f dco_current f out hsdv ? n1 ? 5.000000000 ghz == f xtal f dco_current rfreq current -------------------------------------- - 114.285 mhz == f dco_new f out_new hsdv new ? n1 new ? 161.1328125 mhz 4 ? 8 ? 5.156250000 ghz = == rfreq new f dco_new f xtal ---------------------- - 45.11746934 0x2d1e12788 = ==
si570/si571 16 rev. 1.2 3.2. i 2 c interface the control interface to the si570 is an i 2 c-compatible 2-wire bus for bidirectional communication. the bus consists of a bidirectional serial data line (sda) and a serial clock input (scl). both lines must be connected to the positive supply via an external pullup.fast mode operation is supported for transfer rates up to 400 kbps as specified in the i 2 c-bus specification standard. figure 5 shows the command format for both read and write access. data is always sent msb. data length is 1 byte. read and write commands support 1 or more data bytes as illustrated. the master must send a not acknowledge and a stop after the last read data byte to terminate the read command. the timing specifications and timing diagram for the i2c bus can be found in the i2c-bus specification standard (fast mode operation). the device i2c address is specified in the part number. figure 5. i 2 c command format from master to slave from slave to master a ? acknowledge (sda low) n ? not acknowledge (sda high). required after the last data byte to signal the end of the read comand to the slave. s ? start condition p ? stop condition p a a byte address a s slave address 0 data write command (optional 2 nd data byte and acknowledge illustrated) a byte address a s slave address 0 s slave address 1 a a data a data data n p read command (optional data byte and acknowledge before the last data byte and not acknowledge illustrated)
si570/si571 rev. 1.2 17 4. serial port registers note: any register not listed here is reserved and must no t be written. all bits are r/w unless otherwise noted. register name bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 7 high speed/ n1 dividers hs_div[2:0] n1[6:2] 8 reference frequency n1[1:0] rfreq[37:32] 9 reference frequency rfreq[31:24] 10 reference frequency rfreq[23:16] 11 reference frequency rfreq[15:8] 12 reference frequency rfreq[7:0] 135 reset/freeze/ memory control rst_reg newfreq freeze m freeze vcadc recall 137 freeze dco freeze dco
si570/si571 18 rev. 1.2 register 7. high speed/n1 dividers bitd7d6d5d4d3d2d1d0 name hs_div[2:0] n1[6:2] type r/w r/w bit name function 7:5 hs_div[2:0] dco high speed divider. sets value for high speed divider that takes the dco output f osc as its clock input. 000 = 4 001 = 5 010 = 6 011 = 7 100 = not used. 101 = 9 110 = not used. 111 = 11 4:0 n1[6:2] clkout output divider. sets value for clkout output divider. a llowed values are [1] and [2, 4, 6, ..., 2 7 ]. illegal odd divider values will be rounded up to t he nearest even value. t he value for the n1 reg- ister can be calculated by taking the divider ratio minus one. for example, to divide by 10, write 0001001 (9 decimal) to the n1 registers. 0000000 = 1 1111111 = 2 7 register 8. reference frequency bitd7d6d5d4d3d2d1d0 name n1[1:0] rfreq[37:32] type r/w r/w bit name function 7:6 n1[1:0] clkout output divider. sets value for clkout output divider. a llowed values are [1, 2, 4, 6, ..., 2 7 ]. illegal odd divider values will be rounded up to the neare st even value. the va lue for the n1 regis- ter can be calculated by taking the divider ratio minus one. for example, to divide by 10, write 0001001 (9 decimal) to the n1 registers. 0000000 = 1 1111111 = 2 7 5:0 rfreq[37:32] reference frequency. frequency control input to dco.
si570/si571 rev. 1.2 19 register 9. reference frequency bitd7d6d5d4d3d2d1d0 name rfreq[31:24] type r/w bit name function 7:0 rfreq[31:24] reference frequency. frequency control input to dco. register 10. reference frequency bitd7d6d5d4d3d2d1d0 name rfreq[23:16] type r/w bit name function 7:0 rfreq[23:16] reference frequency. frequency control input to dco. register 11. reference frequency bitd7d6d5d4d3d2d1d0 name rfreq[15:8] type r/w bit name function 7:0 rfreq[15:8] reference frequency. frequency control input to dco.
si570/si571 20 rev. 1.2 reset settings = 00xx xx00 register 12. reference frequency bitd7d6d5d4d3d2d1d0 name rfreq[7:0] type r/w bit name function 7:0 rfreq[7:0] reference frequency. frequency control input to dco. register 135. reset/freeze/memory control bitd7d6d5 d4 d3d2d1d0 name rst_reg newfreq freeze m freeze vcadc n/a recall type r/w r/w r/w r/w r/w r/w bit name function 7 rst_reg internal reset. 0 = normal operation. 1 = reset of all internal logic. output trista ted during reset. upon completion of internal logic reset, rst_reg is interna lly reset to zero. note: asserting rst_reg will interrupt the i 2 c state machine. it is not the recommended approach for starting from initial conditions. 6 newfreq new frequency applied. alerts the dspll that a new frequency configurat ion has been applie d. this bit will clear itself when the new frequency is applied. 5 freeze m freezes the m control word. prevents interim frequency change s when writing rfreq registers. 4freeze vcadc freezes the vc adc output word. may be used to hold the nominal output frequency of an si571. 3:1 n/a always zero. 0 recall recall nvm into ram. 0 = no operation. 1 = write nvm bits into ram. bit is interna lly reset following comp letion of operation. note: asserting recall reloads the nvm contents in to the operating registers without interrupting the i 2 c state machine. it is the recommended approach for starting from initial conditions.
si570/si571 rev. 1.2 21 reset settings = 00xx xx00 register 137. freeze dco bitd7d6d5d4d3d2d1d0 name freeze dco type r/w bit name function 7:5 reserved 4 freeze dco freeze dco. freezes the dspll so the frequency configuration can be modified. 3:0 reserved
si570/si571 22 rev. 1.2 5. si570 (xo) pin descriptions table 13. si570 pin descriptions pin name type function 1 nc n/a no connect. make no external connection to this pin. 2 oe input output enable: see "7. ordering information" on page 24. 3 gnd ground electrical and case ground. 4 clk+ output oscillator output. 5 clk? (nc for cmos*) output (n/a for cmos*) complementary output. (nc for cmos*). 6 v dd power power supply voltage. 7 sda bidirectional open drain i 2 c serial data. 8 scl input i 2 c serial clock. *note: cmos output option only: make no external connection to this pin. (top view) 1 2 3 6 5 4 nc gnd oe v dd clk+ clk? sda scl 8 7
si570/si571 rev. 1.2 23 6. si571 (vcxo) pin descriptions table 14. si571 pin descriptions pin name type function 1 v c analog input control voltage 2 oe input output enable: see "7. ordering information" on page 24. 3 gnd ground electrical and case ground 4 clk+ output oscillator output 5 clk? (nc for cmos*) output (n/a for cmos*) complementary output. (nc for cmos*). 6 v dd power power supply voltage 7 sda bidirectional open drain i 2 c serial data 8 scl input i 2 c serial clock *note: cmos output option only: make no external connection to this pin. (top view) 1 2 3 6 5 4 v c gnd oe v dd clk+ clk? sda scl 8 7
si570/si571 24 rev. 1.2 7. ordering information the si570/si571 supports a wide variety of options including frequency range, start-up frequency, temperature stability, tuning slope, output format, and v dd . specific device configurations are programmed into the si570/si571 at time of shipment. confi gurations are specified using the part number configuratio n chart shown below. silicon labs provides a web browser-based part number conf iguration utility to simplif y this process. refer to www.silabs.com/vcxopartnumber to access this tool and for further ordering instructions. the si570/si571 xo/ vcxo series is supplied in an industry-standard, rohs compliant, 8-pad, 5 x 7 mm package. tape and reel packaging is an ordering option. figure 6. part number convention 570 programmable xo product family 57x x 1 st option code v dd output format output enable polarity a 3.3 lvpecl high b 3.3 lvds high c 3.3 cmos high d3.3cml high e 2.5 lvpecl high f 2.5 lvds high g 2.5 cmos high h2.5cml high j 1.8 cmos high k1.8cml high m 3.3 lvpecl low n 3.3 lvds low p 3.3 cmos low q 3.3 cml low r 2.5 lvpecl low s 2.5 lvds low t 2.5 cmos low u 2.5 cml low v 1.8 cmos low w 1.8 cml low note : cmos available to 160 mhz. 571 programmable vcxo product family r = tape & reel blank = trays operating temp range (c) g ?40 to +85 c device revision letter x d g r six-digit start-up frequency/i 2 c address designator the si57x supports a user-defined start-up frequency within the following bands of frequencies: 10?945 mhz, 970?1134 mhz, and 1213?1417 mhz. the start-up frequency must be in the same frequency range as that specified by the frequency grade 3 rd option code. the si57x supports a user-defined i 2 c 7-bit address. each unique start-up frequency/i 2 c address combination is assigned a six-digit numerical code. this code can be requested during the part number request process. refer to www.silabs.com/vcxopartnumber to request an si57x part number. x xxx xxx 3 rd option code frequency grade code frequency range supported (mhz) a 10-945, 970-1134, 1213-1417.5 b 10-810 c 10-280 (cmos available to 160 mhz) 2 nd option code temperature tuning slope minimum apr stability kv (ppm) for vdd @ code ppm (max) ppm/v (typ) 3.3 v 2.5 v 1.8 v a 100 180 100 75 25 b 100 90 30 note 6 note 6 c 50 180 150 125 75 d50 90 803025 e 20 45 25 note 6 note 6 f 50 135 100 75 50 g 20 356 375 300 235 h 20 180 185 145 105 j 20 135 130 104 70 k 100 356 295 220 155 m 20 33 12 note 6 note 6 notes: 1. for best jitter and phase noise performance, always choose the smallest kv that meets the application?s minimum apr requirements. unlike saw-based solutions which require higher higher kv values to account for their higher temperature dependence, the si55x series provides lower kv options to minimize noise coupling and jitter in real- world pll designs. see an255 and an266 for more information. 2. apr is the ability of a vcxo to track a si gnal over the product lifetime. a vcxo with an apr of 25 ppm is able to lock to a clock with a 25 ppm stability over 15 years over all operating conditions. 3. nominal pull range () = 0.5 x v dd x tuning slope. 4. nominal absolute pull range ( apr) = pull range ? stability ? lifetime aging = 0.5 x v dd x tuning slope ? stability ? 10 ppm 5. minimum apr values noted above include worst case values for all parameters. 6. combination not available. si570 si571 2 nd option code code temperature stability (ppm, max, ) total stablility (ppm, max, ) a 50 61.5 b 20 31.5
si570/si571 rev. 1.2 25 8. si57x mark specification figure 7 illustrates the mark spec ification for the si 57x. table 15 lists the line information. figure 7. mark specification table 15. si57x top mark description line position description 1 1?10 ?silabs?+ part family number, 5xx (first 3 characters in part number) 2 1?10 si570, si571: option1 + option2 + option3 + confignum(6) + temp 3 trace code position 1 pin 1 orientation mark (dot) position 2 product revision (d) position 3?6 tiny trace code (4 alphanumeric charac ters per assembly release instructions) position 7 year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) position 8?9 calendar work week number (1?53), to be assigned by assembly site position 10 ?+? to indicate pb-free and rohs-compliant silabs 123 123 4 5 6 r t t t t y w w + 1 2 3 4 5 6 7 8 9 0
si570/si571 26 rev. 1.2 9. outline diagram and suggested pad layout figure 8 illustrates the package details for the si570/si5 71. table 16 lists the values for the dimensions shown in the illustration. figure 8. si570/si571 outline diagram table 16. package diagram dimensions (mm) dimension min nom max a 1.50 1.65 1.80 b 1.30 1.40 1.50 b1 0.90 1.00 1.10 c 0.50 0.60 0.70 c1 0.30 ? 0.60 d 5.00 bsc d1 4.30 4.40 4.50 e 2.54 bsc e 7.00 bsc e1 6.10 6.20 6.30 h 0.55 0.65 0.75 l 1.17 1.27 1.37 l1 1.07 1.17 1.27 p 1.80 ? 2.60 r0 . 7 0 r e f aaa ? ? 0.15 bbb ? ? 0.15 ccc ? ? 0.10 ddd ? ? 0.10 eee ? ? 0.05 note: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ?
si570/si571 rev. 1.2 27 10. 8-pin pcb land pattern figure 9 illustrates the 8-pin pcb land pattern for the si570/si571. table 17 lists the values for the dimensions shown in the illustration. figure 9. si570/si571 pcb land pattern table 17. pcb land pattern dimensions (mm) dimension min max d2 5.08 ref d3 5.705 ref e 2.54 bsc e2 4.20 ref gd 0.84 ? ge 2.00 ? vd 8.20 ref ve 7.30 ref x1 1.70 typ x2 1.545 typ y1 2.15 ref y2 1.3 ref zd ? 6.78 ze ? 6.30 note: 1. dimensioning and tolerancing per the ansi y14.5m-1994 specification. 2. land pattern design follows ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). 4. controlling dimension is in millimeters (mm).
si570/si571 28 rev. 1.2 d ocument c hange l ist revision 0.2 to revision 0.3 ? updated table 1, ?recommended operating conditions,? on page 5. ?? device maintains stable operation over ?40 to +85 oc operating temperature range. ?? supply current specifications updated. ? updated table 4, ?clk output levels and symmetry,? on page 7. ?? updated lvds differential peak-peak swing specifications. ? updated table 5, ?clk output phase jitter (si570),? on page 7. ? updated table 6, ?clk output phase jitter (si571),? on page 8. ? updated table 7, ?clk output period jitter,? on page 10. ?? revised period jitter specifications. ? updated table 10, ?absolute maximum ratings,? on page 11 to reflect the soldering temperature time at 260 oc is 20?40 sec per jedec j-std-020c. ? updated device programming procedure in section "3.2.3. programming procedure" on page 12. ? updated "7. ordering information" on page 24. ?? changed ordering instructions to revision d. ? added "8. si57x mark specification" on page 25. revision 0.3 to revision 0.31 ? updated "3.2.3. programming procedure" on page 12. ?? corrected step 6 to read ?bit 4?. ? corrected freeze dco bit location in register 137 to bit 4 on pages 14 and 18. revision 0.31 to revision 1.0 ? updated " functional block diagram" on page 1. ? updated figure 1, ?si570 detailed block diagram,? on page 4. ? updated figure 2, ?si571 detailed block diagram,? on page 4. ? updated figure 6, ?part number convention,? on page 24. ? updated table 1, ?recommended operating conditions,? on page 5. ? updated table 3, ?clk output frequency characteristics,? on page 6. ? updated table 6, ?clk output phase jitter (si571),? on page 8. ? updated table 12, ?programming constraints and timing,? on page 12. ? updated table 12, ?programming constraints and timing,? on page 12. ? updated "3. functional description" on page 13. ? updated "3.1. progra mming a new output frequency" on page 13. ? updated "3.1.1. reconfiguri ng the output clock for a small change in frequency" on page 13. ? updated "3.1.2. reconfiguring the output clock for large changes in output frequency" on page 14. ? updated ?7.ordering information?. ?? updated figure 6, ?part number convention,? on page 24. revision 1.0 to revision 1.1 ? restored programming constraint information on page 15 and in table 12, page 12. ? clarified nc (no connect) pin designations in tables 13?14 on pages 22?23. revision 1.1 to revision 1.2 ? replaced ?unfreeze to newfreq delay? with the clearer terminology ?unfreeze to newfreq timeout? on page 15 and in table 12 on page 12. ? added freeze m procedure on page 14 for preventing output clock changes during small frequency change multi-register rfreq writes. ? added freeze m, freeze vcadc, and rst_reg versus recall information to register 135 references in "4. serial port registers" on pages 17 and 20. ? updated figure 8 and table 16 on page 26 to include production test sidepads. this change is for reference only as the sidepads are raised above the seating plane and do not impact pcb layout. ? corrected errors in table 11 on page 12.
si570/si571 rev. 1.2 29 n otes :
si570/si571 30 rev. 1.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/p ages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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